Verilog Design of Media Compression Modules

We are sorry, this position has been filled.

In this project, the student will design, implement, and optimize media compression kernels (audio and video) in a hardware description language (Verilog). The objective is to find flexible, performant, and energy efficient ways of compressing media.

Lab: ARCADE Lab

Direct Supervisor: Martha Kim

Position Dates: 6/1/2018 - 8/31/2018

Hours per Week: 40

Paid Position: Yes

Credit: No

Qualifications: Verilog Hardware Description Language

Eligibility: Junior, Senior; SEAS only