(BNL) Deterministic Ethernet Accelerator Type Timing Systems on a Standalone FPGA


The NSLS_II has used a commercial Timing system from a Finnish company for the bulk of the accelerator timing needs. This can also used on beamlines for time resolved experiments. The current solution provides a highly sophisticated nano second resolution event generator and event receiver paired one to many in order receive and distribute timing signals “downstream”. It is possible to replicate this functionality of systems on low end commodity hardware, now available from the FPGA Vendors.

Thwe bulk of this work has already been performed by the Beam position processors as developed by NSLS_II and latterly by the ALS at Berkeley. This project involves refactoring this code into a smaller FPGA Design and providing it as a stand alone timing element that can be deployed quickly and cost effectively on beamlines where time resolved experiments or even main phase matching.

Position Dates: 6/5/2017 - 8/11/2017

Paid Position: Yes, hourly pay rate dependent on student's class level

Note: Housing may be available

Qualifications: Board design skills, FPGA hardware and some software skills are all required.

Eligibility: U.S. Citizens, Permanent Residents, and international students.